The present invention relates generally to transistors and more particularly to metal oxide semiconductor transistors.
Complementary metal oxide semiconductor (CMOS) transistors have received wide acceptance in digital circuitry because of the relatively small amount of power required thereby and the relatively high packing densities thereof, enabling many devices to be formed on a single integrated circuit (IC) chip. One transistor of a CMOS pair is formed by diffusing a relatively deep semiconductor well into a semiconductor substrate. A channel is formed in the well by diffusing two spaced layers into the well. An oxide layer covers the well and a portion of the two layers. Ohmic contacts are formed by metallizing the two diffusion layers comprising the channel and the oxide layer, whereby source, drain and gate electrodes are provided. The other, complementary transistor is formed by diffusing a pair of layers into the substrate to form a second channel. An oxide layer covers the second channel, as well as a portion of the two diffused layers of the second transistor. Ohmic metallized contacts are formed on the diffused layers and over the oxide of the semiconductor to provide the source, drain and gate electrodes of the second transistor. The gate electrodes of the two transistors are connected together.
Problems with the conventional prior art devices are: (1) a relatively slow response time, (2) relatively low transconductance which results in low gain, and (3) low breakdown voltage in response to the signal applied to the gate electrodes.
In one improved conventional prior art device a CMOS integrated circuit utilizes a symmetrical double diffused N-channel metal oxide semiconductor (DMOS) transistor and a P-channel metal oxide semiconductor (MOS) transistor. The response time of such a CMOS is limited by slow response time of the P-channel MOS, which is one of the aforementioned problems with conventional prior art devices. Because of the symmetrical properties of the DMOS, charged carriers flowing across the channel are both accelerated and decelerated causing a further response time impairment. The described CMOS integrated circuit appears to have improved packing density characteristics relative to the conventional CMOS, is easier to fabricate than the conventional CMOS, and has a faster response time than the conventional CMOS.
It has been previously realized that improved response times in MOS transistors can be obtained by employing an asymmetrical double diffused channel. In an asymmetrical DMOS transistor, a channel exists in the substrate between a pair of diffused layers (the double diffused layers) and a single diffused layer. A source region is formed by first diffusing a relatively low concentration P type dopant into a lightly doped or intrinsic substrate. Into the P layer is diffused an N+ layer that is completely surrounded by the P diffused layer. The drain region is formed by diffusing N+ dopant into the substrate, whereby the channel subsists between the P diffused layer and the N+ layer of the drain region. The asymmetrical, DMOS has a relatively fast response time because charged particles, as they flow across the channel, are only accelerated to the drain electrode; there is no deceleration and acceleration of the charged particles as they flow across the channel, as exists in the symmetrical DMOS. Attempts to form a CMOS out of a pair of opposite conductivity DMOS' have not been successful because of the cumbersomeness of the resulting structure, causing low packing densities and difficulties in fabrication.